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NTHS5404 Power MOSFET
20 V, 7.2 A, N-Channel ChipFETE
Features
* * * *
Low RDS(on) for Higher Efficiency Logic Level Gate Drive Miniature ChipFET Surface Mount Package Saves Board Space Pb-Free Package is Available
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V(BR)DSS 20 V
RDS(on) TYP 25 mW @ 4.5 V
ID MAX 7.2 A
Applications
* Power Management in Portable and Battery-Powered Products; i.e.,
Cellular and Cordless Telephones and PCMCIA Cards
D
MAXIMUM RATINGS (TA = 25C unless otherwise noted)
Rating Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150C) (Note 1) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Diode Conduction) (Note 1) Maximum Power Dissipation (Note 1) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID 7.2 5.2 IDM IS PD 2.5 1.3 TJ, Tstg 1.3 0.7 C 7.2 "20 5.2 5.2 3.8 A A W 5 Secs 20 "12 Steady State Unit V V A ChipFET CASE 1206A STYLE 1 S N-Channel MOSFET G
PIN CONNECTIONS
D D D S
8 7 6 5 1 2 3 4
MARKING DIAGRAM
1 2 3 4 A2 M 8 7 6 5
D D D G
-55 to +150
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
A2 = Specific Device Code M = Month Code
ORDERING INFORMATION
Device NTHS5404T1 NTHS5404T1G Package ChipFET ChipFET (Pb-Free) Shipping 3000/Tape & Reel 3000/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
October, 2004 - Rev. 3
Publication Order Number: NTHS5404T1/D
NTHS5404
THERMAL CHARACTERISTICS
Characteristic Maximum Junction-to-Ambient (Note 2) t v 5 sec Steady State Maximum Junction-to-Foot (Drain) Steady State Symbol RqJA Typ 40 80 15 Max 50 95 20 C/W Unit C/W
RqJF
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic Static Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS VDS = VGS, ID = 250 mA VDS = 0 V, VGS = "12 V VDS = 16 V, VGS = 0 V VDS = 16 V, VGS = 0 V, TJ = 85C On-State Drain Current (Note 3) Drain-Source On-State Resistance (Note 3) ID(on) rDS(on) () VDS w 5.0 V, VGS = 4.5 V VGS = 4.5 V, ID = 5.2 A VGS = 2.5 V, ID = 4.3 A Forward Transconductance (Note 3) Diode Forward Voltage (Note 3) Dynamic (Note 4) Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time QG QGS QGD td(on) tr td(off) tf trr IF = 1.1 A, di/dt = 100 A/ms VDD = 10 V, RL = 10 W ID ^ 1.0 A, VGEN = 4 5 V 10A 4.5 V, RG = 6 W VDS = 10 V, VGS = 4.5 V, ID = 5.2 A - - - - - - - - 12 2.4 3.2 20 40 40 15 30 18 - - 30 60 60 23 60 ns nC gfs VSD VDS = 10 V, ID = 5.2 A IS = 5.2 A, VGS = 0 V 0.6 - - - 20 - - - - - - - - - 0.025 0.038 20 0.8 - "100 1.0 5.0 - 0.030 0.045 - 1.2 S V A W V nA mA Symbol Test Condition Min Typ Max Unit
2. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.
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NTHS5404
TYPICAL ELECTRICAL CHARACTERISTICS
12 ID, DRAIN CURRENT (AMPS) 10 VGS = 2 V - 5 V 8 1.6 V 6 4 1.4 V 2 VGS = 1.2 V 0 0 0.5 1 1.5 2 2.5 3 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0 0 0.5 1 1.5 2 2.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C
5V
2V
1.8 V ID, DRAIN CURRENT (AMPS)
12 10 8 6 4 125C 2 25C TC = -55C
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.06 0.05 0.04 0.03 0.02 0.01 0 0 1 2 3 4 5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) ID = 5.2 A TJ = 25C 0.040 0.038 0.036 0.034 0.032 0.030
Figure 2. Transfer Characteristics
TJ = 25C
VGS = 2.5 V
VGS = 4.5 V 0.028 0.026 0.024 2 3 4 5 6 7 8 9 10 ID, DRAIN CURRENT (AMPS) VGS = 6 V
Figure 3. On-Resistance versus Gate-to-Source Voltage
1.6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) ID = 5.2 A VGS = 4.5 V IDSS, LEAKAGE (AMPS) 1.4 1E-06 1E-05
Figure 4. On-Resistance versus Drain Current and Gate Voltage
VGS = 0 V
1.2
TJ = 150C TJ = 100C
1
1E-07
0.8 0.6 -50
1E-08 -25 0 25 50 75 100 125 150 0 4 8 12 16 20 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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NTHS5404
TYPICAL ELECTRICAL CHARACTERISTICS
VDS, DRAIN-TO-SOURCE VOLTAGE (V) 5 VGS, GATE-TO-SOURCE VOLTAGE (V) 1800 C, CAPACITANCE (pF) 1500 1200 900 600 300 0 12 8 4 VGS 0 VDS 4 8 12 16 20 Coss Crss Ciss VDS = 0 V VGS = 0 V TJ = 25C QG 11 10 9 8 7 6 5 QGD QGS ID = 5.2 A TJ = 25C QGD/QGS = 1.33 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 QG, TOTAL GATE CHARGE (nC)
4
3
2
1
0
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
100 td(off) tf t, TIME (ns) IS, SOURCE CURRENT (AMPS) 5
Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge
4
VGS = 0 V TJ = 25C
3
10
td(on) tr VDD = 10 V ID = +1.0 A VGS = 4.5 V
2
1 0
1 1 10 RG, GATE RESISTANCE (OHMS) 100
0
0.2
0.4
0.6
0.8
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation versus Gate Resistance
Figure 10. Diode Forward Voltage versus Current
NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE
1 Duty Cycle = 0.5
0.2 0.1 0.05 0.02 Single Pulse 0.0001 0.001 0.01 0.1 1 10 100 1000 t2 DUTY CYCLE, D = t1/t2 t1 PDM
PER UNIT BASE = RqJA = 80C/W TJM - TA = PDMZqJA(t) SURFACE MOUNTED
0.1
0.01 SQUARE WAVE PULSE DURATION (sec)
Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient
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NTHS5404
SOLDERING FOOTPRINT*
2.032 0.08 0.457 0.018 0.635 0.025 1.727 0.068 2.032 0.08
0.457 0.018 0.711 0.028 0.66 0.026 0.66 0.026 0.711 0.028
0.178 0.007
Figure 12. Basic
Figure 13. Style 1
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 12. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 13 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper lead-frame) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.
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NTHS5404
PACKAGE DIMENSIONS
ChipFETTM CASE 1206A-03 ISSUE E
A
8 7 6 5
M K
5 6 3 7 2 8 1
S
1 2 3 4
B
4
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. 7. 1206A-01 AND 1206A-02 OBSOLETE. NEW STANDARD IS 1206A-03. DIM A B C D G J K L M S MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.20 0.28 0.42 0.55 BSC 5 NOM 1.80 2.00 DRAIN DRAIN DRAIN GATE SOURCE DRAIN DRAIN DRAIN INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.011 0.017 0.022 BSC 5 NOM 0.072 0.080
L G
D
J
C 0.05 (0.002)
STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8.
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NTHS5404T1/D

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